IEEE International Conference on Computer - Aided Design , pp . 546 - 549 , November 1991 Methods for Reducing Events in Sequential Circuit

Methods for Reducing Events in Sequential Circuit Fault Simulation Elizabeth M. Rudnick Thomas M. Niermann Janak H. Patel Center for Reliable and Sunrise Test Systems Inc. Center for Reliable and High-Performance Computing Sunnyvale, CA 94086 High-Performance Computing University of Illinois University of Illinois Urbana, IL 61801 Urbana, IL 61801 Abstract Methods are investigated for reducing events in sequential circuit fault simulation by reducing the number of faults simulated for each test vector. Inactive faults, which are guaranteed to have no e ect on the output or the next state, are identi ed using local information from the fault-free circuit in one technique. In a second technique, the StarAlgorithm is extended to handle sequential circuits and provide global information about inactive faults, based on the fault-free circuit state. Both techniques are integrated into the PROOFS synchronous sequential circuit fault simulator. An average 28% reduction in faulty circuit gate evaluations is obtained for the 19 ISCAS-89 benchmark circuits studied using the rst technique, and 33% reduction for the two techniques combined. Execution times decrease by an average of 17% when the rst technique is used. For the largest circuits, further improvements in execution time are made when the Star-Algorithm is included.